Sub-Surface Damage Removal in Fabrication & Polishing of Silicon Carbide

Silicon Carbide (SiC) is emerging as a promising substrate for systems which leverage the low lattice mismatch with Gallium Nitride (GaN), high power density, heat dissipation and radiation hardness properties unique to this semiconductor. Wafer fabrication and polishing of SiC substrates poses processing issues as a result of the material’s high Mohs hardness (~9.25), and chemical inertness. Particularly important to epitaxial layer nucleation on these wafer surfaces is an atomically smooth finish free of subsurface damage, which is invisible to most inspection methods. Prime damage-free surfaces will ideally exhibit bi-layer terraces corresponding to plane (0001) edges. II-VI has achieved such damage-free surfaces by closely monitoring damage through molten KOH etching and optical characterization, and developing a chemo-mechanical polish (CMP) process that effectively reveals this damage while simultaneously removing it. ORIGIN AND CHARACTERIZATION OF SUB-SURFACE DAMAGE AFTER MECHANICAL POLISHING Mechanical polishing of SiC is typically done with diamond based slurries, where the abrasive size is successively reduced and eventually ending with a submicron slurry to achieve the desired roughness. Surfaces with low average roughness (Ra < 5Å) can be achieved (see Figure 1) relatively easily. These surfaces can be featureless or show some minimal polishing damage under AFM microscopy. However, after high-temperature thermal processing prior to or during epitaxial growth, a dense network of scratches and defects can be revealed. This network corresponds to the sub-surface damage or dislocation network impacted into the SiC surface during the mechanical abrasion process. Figure 2 shows an optical microscope picture of a thermally treated surface, which previously exhibited roughness typical of Figure 1 before thermal etching. Scratch depth invisible to the eye can be revealed to be as high as 150Å. However, this damage can be revealed in-situ during either metal organic chemical Fig 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 1 2 3 4 5 6 7 8 9 10 Cumulative Take-off in um Et ch R at e um /m in Damage-free etch rate Figure 3: Etch Rate in KOH @450°C of a mechanically polished SiC wafer as a function of material removed showing reduction in etch rate with time. Figure 1: Typical wafer surface after final mechanical process (Zygo® normal white light interferometry) ure 2: Thermal Revelation of Sub-Surface Damage (350 x 260μm) at ~1600°C. vapor deposition (MOCVD) growth during an initial hydrogen purge at high temperature, or more drastically during molecular beam epitaxy (MBE) by 3-dimensional preferential growth around such defects. As with other semiconductors, this sub-surface damage can easily be revealed by selective etching. However in the absence of a room temperature selective etch for SiC, molten salt etching is often employed. II-VI has made use of a previously established molten KOH etching [1] technique to expose and characterize this subsurface damage. In our case, etching is carried out at 450°C within a nickel crucible inside a vertical ceramic furnace. As is evident in the example of Figure 3, the etch rate is much higher in the damaged surface region and reduces quickly, approaching an asymptotic rate (shown as dotted horizontal line in figure) as the damage is removed after a few microns. Using this etch technique, the depth of damage can easily be assessed at every stage in the process. Damage can thereby be reduced to a minimum by careful attention to the normal array of polishing process parameters available (slurry types, sizes, proper distributions, pressures, rotation rates etc). Minimization of sub-surface damage after the final stage of the mechanical polishing process to <150Å is routinely achieved (see Figure 4). SUB-SURFACE DAMAGE REMOVAL IN SIC Chemical-mechanical polishing is often the last and most critical step in the polishing process of many semiconductors such as Si and GaAs. In these materials the process utilizes the combination of a chemical oxidation reaction followed by mechanical abrasion or secondary chemical reaction. The continuous and simultaneous friction and chemical attack leads to material removal resulting in extremely planar surfaces with zero or near zero sub-surface damage, as the abrasive can be of significantly lower hardness than the non-affected substrate material. Unfortunately in the case of SiC, its combined chemical inertness and hardness leads to very low removal rates during conventional CMP techniques such that subsurface damage cannot be removed in a timely manner. Additionally, a directly proportional relationship has been indicated with respect to wafer surface orientation. As surfaces approach a perfectly planar (0001) or “c” plane, process time increases appreciably, as fewer planar edges a C r C M P 7 a Max a Min a Ave